ACT: A Cluster Co-Processor for 3G Baseband Wireless

— Architectures for wireless systems have traditionally been designed to meet real-time requirements, t on a limited die area, and operate within a low power budget. These conditions are usually met by implementing compute-intensive operations in an application speci c integrated circuit (ASIC). ASIC design is both expensive and time consuming. ASICs also suffer in that even minor evolutionary changes in the application invoke another ASIC design cycle. In the rapidly evolving wireless communication space these defects are severe. Flexibility can be achieved by recon gurable architectures, and the ability to use special purpose con gurations enhance both performance and energy ef ciency. Often recon gurable systems are based on FPGA devices which compromise both logic speed and power in order to achieve recon gurability. This work introduces a nonFPGA based execution cluster and it’s CMOS implementation which serves as a recon gurable coprocessor for wireless applications. The approach is compared against equivalent functionality provided by either an embedded microprocessor running code and an ASIC. The evaluation is done using several key 3G cellular telephony applications. The result is that the coprocessor approach is able to achieve an order of magnitude improvement in performance while also reducing energy consumption by an order of magnitude over the general purpose microprocessor approach while retaining a reasonable level of generality. Index Terms— VLSI, VLIW, PROCESSORS, LOW POWER. EDICS Category: 5-VARC, 5-VLSI, 5-MICR